Signal redundancy utilizing slope limiting lines



March 28, 1967 E. B. GLOVER 3,311,909

SIGNAL REDUNDANCY UTILIZING SLOPE LIMITING LINES Filed Aug. 5. 1964 2Sheets-Sheet l memos A M 316-3 \NPUT i ANALOG OUTPUT 2R 4R 8R \6R as 84as r as A a A e A.G A a r-- fa"! 88 1 a9 1 T INVENTOR ATTORNEYS UnitedStates Patent Office 3,311,909 SIGNAL REDUNDANCY UTILIZING SLOPELHMITHNG LINES Edward B. Glover, Melbourne Beach, Fla, assignor toRadiation Incorporated, Melbourne, Plan, a corporation of Florida FiledAug. 5, 1964, Ser. No. 387,562 5 Claims. (Cl. 340-345) The presentinvention relates generally to telemetry systems and more particularlyto variable transmission rate telemetry systems wherein data istransmitted only when the event being monitored lies outside a pair ofupper and lower slope limiting lines or fans.

The requirement for effective systems wherein redundancy in datatransmitted from missiles is considerably reduced has receivedconsiderable attention. Since missile and space craft data handlingsystems are generating larger and larger amounts of data, as the sizeand complexity of the missiles and space craft increase, the telemetrylinks between these devices and the ground receiver are requiringunreasonably wide bandwidths. Wide bandwidth is necessary because everymonitored parameter is sampled at a constant rate that is at least twicethe highest frequency of any parameter. As the number of monitoredchannels increases, the sampling rate must be increased to satisfy theabove requirement. Increasing the data sampling rate requires wider bandwidth links so that a compromise between bandwidth and the amount ofinformation transmitted must be reached.

The present invention affords relief from this dilemma by relying uponthe fact that the monitored information is, primarily, of a lowfrequency nature. In consequence, according to the present invention,data is transmitted at a rate determined by the frequency of themonitored event. If the monitored data is following a predetermined lawof variation, within bounds, no signals are transmitted until the dataexceeds those bounds. Thereby, redundant data, i.e. data having nosignificant information content outside the bounds known at the receiverfrom the predetermined variation law, is not transmitted and datatransmission efficiency is considerably increased. At the receiver, thedata points are collected and the parameter at the transmitter isascertained by interpolating, according to the known variation law,between adjacent received points.

In the system of the present invention, the known law of variation isassumed to be a linear function of time. By transmitting data pointsonly when the monitored parameter differs from a particular linearfunction, the receiver can reconstitute the monitored parameter bylinearly interpolating between the transmitted points.

According to the present invention, a series of upper and lower slopelimiting lines or fans are produced between the first sample y of aninterval and points y ifi If y lies outside the limits defined by theseconverging lines, y is considered as non-redundant, hence istransmitted. To insure converging of the limiting lines even though theevent being monitored changes slope direction, the slopes of adjacentlimiting lines are compared and the successive line is taken as thelimit only if it will result in convergence.

It is, accordingly, an object of the present invention to provide avariable transmission rate telemetry system wherein only non-redundantdata is transmitted.

Another object of the invention is to provide a telemetry system whereindata is transmitted only when it dif- 3-,3l LWQ Patented Mar. 28, 1967fers from a known law of variation by a predetermined amount.

A further object of the invention is to provide a telemetry systemwherein data is transmitted only when the value of an event beingmonitored differs from a linear time function by a predetermined value.

A further object of the invention is to provide a telemetry systemwherein data is transmitted only when the value of an event beingmonitored falls outside the limits defined by a pair of lines thatconverge to a line determined by the sampled values.

An additional object of the invention is to provide a telemetry systemthat enables low bandwidth operation, wherein maximum information istransmitted by relying only upon the utilization of non-redundant data.

The above and still further objects, features and advantages of thepresent invention will become apparent upon consideration of thefollowing detailed description of one specific embodiment thereof,especially when taken in conjunction with the accompanying drawings,wherein:

FIGURE 1 is a graph to aid in describing a preferred embodiment of theinvention;

FIGURE 2 is a block diagram of the embodiment operating in accordancewith FIGURE 1; and

FIGURE 3 is a circuit diagram of a hybrid divider utilized in thecircuit of FIGURE 2.

Reference is now made to FIGURE 1 of the drawings where the procedurefor determining when a point to be transmitted according to thepreferred embodiment is disclosed. According to this method, the slopesof converging lines drawn between the first point y of function 41 andsuccessive points y 3 etc. at equally spaced times t t etc. along thefunction are compared with the slopes of successively converging linesoriginating at y and intercepting the points y ia, y ia, etc., where 0cis a predetermined vertical increment. A data point y is transmittedwhen the slope of the line between y and y lies outside the converginglines.

In FIGURE 1, a pair of vertical lines 1U and IL are directed upwardlyand downwardly from point y Since these lines define the limits withinwhich y may lie, it becomes apparent that y :may have any value andstill be within the limits of the area to the right of 1U and IL. Thusline 42, the straight line between points y and y has a slope,

y2 /1 ye-1 i -i, At

between the limit lines 1U and IL. New upper and lower limiting lines 2Uand 2L are now drawn from y, to (y +a) and 2Ot), respectively, and line43 is drawn between y and y Since the slope of 2U is less than the slopeof 1U, the former is selected as a new upper limiting line; 2L isselected as a new lower limiting line since its slope is greater thanthat of IL. The slope of line 43,

respectively. This determination is made by ascertaining that m isgreater than m and that m is less than m i.e., m is more positive than mand m is more positive than m In consequence, y is redundant, is notnecessary in determining function 4 1 within the desired system accuracyand need not be transmitted.

Point y.; is now investigated by drawing (1) line 44 be- I tween y and 3and (2) limiting lines 3U and 3L, the first intercepting y and (y +u)and the second intercepting y and (y ot). For the same reasons discussedsupra with regard to selection of 2U and 2L, 3U and 3L are now selectedas the next upper and lower limiting lines. Since the slope of line 44,

y also is redundant.

The lines 45, 4U and 4L are all now drawn from y to intercept the points(y +a) and (y a), respectively. As before, the line 4U it utilize-d toconsider whether the investigated point, y is within the fan of thelimiting lines. The line 4L, however, is not so utilized because itsslope is less than that of 3L, i.e. the slope of 4L is more negativethan the slope of 3L. The retention of line 3L as the lower sloperesults from a requirement that the upper and lower limiting linesalways converge.

Considering whether M is redundant or not, the slope of line 45,

is less than the slope, 111 of SL. Thus, 3 is not within the sectordefined by lines 4U and 3L, so y., is the last point within theconverging fan of limit lines, is non-redundant and must be transmitted.

At the receiver, a straight line is drawn between the transmitted pointsy and to give an approximate indication of the value of function 41between t and it, with a minimum number of transmitted points. If theline 4L, rather than 3L is utilized as the lower limit for y;,, noinformation regarding y would be transmitted since m is greater than mAs a result, the receiver would not be appraised of the rise in function41 as it progresses from [1 t0 [4.

After point M is transmitted, a new computation cycle is initiated usingthat point as the reference in the same manner that y was previouslyemployed.

The apparatus utilized to determine when a point is to be transmittedaccording to the scheme illustrated by FIG. 1 is shown schematically inFIG. 2. A low frequency analog input signal, of the type generated by astrain gage accelerometer on a missile, is applied to analog to digitalconverter 51 via input gate 52. Converter 51 includes an output storageregister from which is derived a parallel, multi-bit binary signalindicative of the analog signal at times t t etc.

The control of signal flow to coder 51 and input gate 52 is in responseto output pulses derived from 19 state sequencer or timer 53. Whileconnections are not drawn between timer 53 and the elements controlledthereby, they are represented by circles having numerals indicative ofthe various timer stages that are connected to the computer componentsby appropriate lines. Thus, input gate 52 is opened and closed inresponse to the first and twelfth timer pulse, respectively, while coder51 is cleared in response to the first timer pulse, has its storage setin response to the second, thirteenth and seventeenth timer pulses, andhas its storage readout to accumulator 53.1 of arithmetic unit 54 andprevious sample register 55.1 when the third and eleventh timer pulsesare respectively derived. Register 55.1 is readout to the transmitterand original sample register 57 only when the nineteenth timing pulse isgenerated.

Arithmetic unit 54 includes an adder logic section 55 that decrementsthe number stored in accumulator 53.1 by the count in number register 56when the fourth and eighth timing pulses are derived. Adder unit 55 isalso responsive to the fifteenth timer pulse in a manner whereby theaccumulator 53.1 is advanced by the count stored in number register 56.Information indicative of the value of the original or first sample ineach sampling sequence is transferred into register 56 from originalsample register 57 in response to the third timing pulse. Register 56 isloaded with numbers indicative of or and 20: from prewired storage whenthe seventh and fourteenth timing pulses are respectively generated. Itis cleared in response to the first, twelfth and nineteenth timingpulses being derived.

The contents of accumulator 53.1 are readout to digital to analogconverter 58 upon the derivation of the fifth, twelfth and sixteenthpulses. Converter 58 applies the most recently readout number ofaccumulator 53.1 as the analog dividend input to high speed hybriddivider 59 except when the converter is being cleared during the first,eleventh and fifteenth timing pulses. The binary divisor input todivider 59, indicative of current time relative to the occurrence timeof the original sample, is applied in parallel from all but the mostsignificant stage of five stage shift register 61 via gates 62.1. Gates62.1 are opened only when a binary one is in the most significant stageof register 61 and when any of the timing pulses between three and sixis generated, as determined by the output of OR gate 63.1.

To enable register 61 to store a time indicating signal, five bit or 32state time counter 64, AND gate 65.1 and delay stage 66.1 are provided.Counter 64 is indexed, i.e. has its count advanced by a binary one, inresponse to the first timing pulse and is reset to a binary one when thenineteenth timing pulse is produced. The count of counter 64 is readout,in parallel, to shift register 61 in response to timing pulse numbertwo. To provide a binary time indication, the contents of register 61are shifted left (e.g. from 0011 to 0100. AND gate 65.1 is enabled onlyin response to a binary zero in the most significant stage of register61. Enabling gate 65.1 couples the output of OR gate 61 through delay66, to the least significant stage of register 61. The amount of delayintroduced by element 66.1 is sutficient to prevent loading of the firststage of register 61 by the last register stage during readout. Thedelay is less than the interval between adjacent timing pulses so thatthe contents of the last stage are in the first stage when the nextpulse from sequencer 53 occurs.

Since the binary divisor input to divider 59 is indicative of time fromthe original sample to the present and the dividend output of converter58 represents the values of points on the function relative to theoriginal sample value, as seen infra, the output of divider 59represents the slopes of the various lines considered in FIG. 1. Theoutput of divider 59 is coupled back to coder 51 through analog gate61.1 when the latter is opened, i.e., when the gate is enabled, betweentermination of timing pulses twelve and eighteen. The slope indicationsderiving from divider 59 are at all times compared in high speed analogcomparison circuit 62 with the upper and lower limit slopes generated bydigital to analog converter 63. Converter 63 is cleared when timingpulses, one, eight and fifteen are generated to enable differentcomparisons to be made with the same circuit during a single computationcycle.

Binary indications of the upper and lower slope limits, 1U, 1L, 2U, 2Letc., are read into converter 63 from shift registers 64 and 65 onlywhen the sixteenth and ninth timing pulses are respectively generated.This is a parallel operation with signals from all stages of eitherregister 64 or 65 being simultaneously read into the correspondingconverter stages. At the beginning of each sampling cycle, i.e. thefirst time a particular original sample is read into register 57, eachstage of registers 64 and 65 is loaded in response to the nineteenthtiming pulse with a binary one and zero, respectively. This providesinitial slope indications commensurate with the lines 1U I. and IL.Lower slope limits are thereafter selectively read into register 65 fromcoder 51 when timing pulse 14 generated, provided the slope, m for thelower limit of the most recently sampled point is greater than theprevious lower limit slope m Comparison circuit 62 and AND gates A and Aare utilized to determine which slope is greater. AND gate A is enabledby the output of circuit 62 on lead 67 and timing pulse fourteen only ifthe ru output of divider 59 is greater than the nz output of converter63. Only when gate A is enabled, is the output of coder 51 coupled toregister 65.

After 1U has been read from register 64, upper slope limits are readinto it from coder 51 via the enabling circuit provided by AND gate AGate A is enabled only when timing pulse eighteen occurs and comparisoncircuit 62 produces an output on lead 66. The latter event occurs whenthe m output of converter 63 is greater than the m output of divider 59.If either of gates A or A is not enabled, the respective register 64 or65 retains the previous slope limits m or m even though the systembegins to analyze a new point, n+1.

The counts stored in registers 64 and 65 are shifted left by one placewhenever a binary count of 10000 is reached by time register 61. Such acounter indicates that time counter 64 is set at 2 where n is anyinteger from zero to four, inclusive. Shifting is accomplished bysampling all five stages of register 61 with AND gate 71 when timingpulses three through six are generated, as determined by OR gate 72. Ifthe most siginficant shift register 61 stage has a binary one and theother four stages have binary zeros when a binary one is produced bygate 72, gate 71 supplies a control pulse to registers 64- and 65 toshift their contents left one place, hence multiply the numbers storedtherein by a decimal two or binary 10. The contents of registers 64.1and 65 are multiplied by two since divider 59 is capable of dividingonly by numbers between one and two, as seen infra. Thus, it isnecessary to multiply the divisor inputs to divider 59 by two, or afactor thereof, Whenever division by two is accomplished.

As a further feature, registers 64 and 65 are maintained at theirmaximum indicating counts 11111, commensurate with the digital number31, even if the slope applied thereto exceeds the maximum registercount. If they are driven or shifted to a point where their mostsignificant stages are driven to overflow, this is sensed by detectors73 and 74. When either detector receives an overflow indication, itsrespective one shot 75 or '76 is activated to load a binary one intoeach stage of the corresponding register. If overflow is not compensatedin this manner, registers 64 and 65 could store numbers considerablyless than 31 even though slopes in excess of 31 are applied thereto.

To determine if the slope m falls outside the upper and lower limitsstored by registers 64 and 65, AND gate A responsive to the signal onlead 66 and timing pulse seven, and AND gate A responsive to the signalon lead 67 and timing pulse 10, are provided. Thereby, gate A is enabledonly when the output of divider 59 exceeds the output of converter 63and vice versa for gate A If m falls outside the upper or lower limits,m or m one of gates A or A is activated. Activation of either gate A orA results in timer 53 being advanced to the nineteenth timing pulse viathe connection from gates A and A through OR gate 78. When timer 53reaches pulse 19 it advances to the third pulse in its sequence. When itreaches pulse eighteen, timer 53 advances directly to pulse one. Theinternal timer circuitry is such that the periods between pulse three ofevery adjacent sampling interval are equal.

An exemplary circuit that can be utilized as hybrid divider S9 isillustrated in FIG. 3. The analog output of converter 58 is appliedthrough amplifier 81 to resistance 82, having a value of R. Betweenresistance 82 and ground, four parallel branches including resistances83-85 are provided. In series with each of resistances 83-86 is aseparate gate 8790, respectively. Each gate is disabled when a binaryzero is applied to it and enabled in response to a binary one. Toprovide division by sixteen equally spaced numbers between one and two,the values of resistances 83-86 are selected as 2R, 4R, SR and 16R,respectively, and gate is responsive to the lowest order binary bitstored in register 61. The remaining gates are responsive to the higherorder binary bits in register 61 according to their reversed numericaldenomination. The division circuit functions to divide the analog inputin accordance with the following table:

Digital Code Input Gate Causes Division by 0 0 0 0 1. 0000 0 0 0 1 1.0625 0 0 1 0 1. 1250 0 0 1 1 1. 1875 0 1 0 O 1. 2500 0 1 0 1 1. 3125 0 11 0 1. 37 0 0 1 1 l 1. 4375 1 0 0 0 1. 5000 1 0 0 1 1. 5625 1 0 1 O 1.6250 1 0 1 1 1. 6875 1 l 0 0 1. 7500 1 1 0 1 1. 8125 1 1 1 0 1. 8750 1 11 1 1. 9375 It is noted from the above table that the analog input tothe divisor is never reduced by more than one half, a desirable featurefor accurate division. The need for higher accuracy is satisfied by thefloating binary point arrangement discussed supra in connection with ANDgate 71 as well as registers 64 and 65.

To provide an indication of how the system of FIGS. 2 and 3 operates,function 41 of FIG. 1 is taken as an example by starting at I It isassumed that y is the original or first sample to be considered in thepresent operation, hence is stored in register 57 and that y is storedin coder 51. Also, assume that counter 64 is set to one, register 64stores ones in every stage, register 65 stores zeros in every stage,accumulator 53 as well as number register are both cleared and thattimer 53 is just being set to step 3, when timing pulse three is aboutto be generated. The manner by which these assumptions are establishedwill be realized as the description proceeds.

When sequencer 53 advances into state three, the value of y stored incoder 51 is transferred to accumulator 53.1. At the same time, ytransferred from register 57 to register 56 and time register 61 isshifted from 00001 to 00010. Sequencer 53 now advances into state fourwhere the contents of accumulator 53.1, are decremented by the number inregister 56, y to give the result y -y =Ay Simultaneously, register 61is shifted left so it stores 00100.

Timing pulse five is now derived to (1) transfer Ay from accumulator53.1 to converter 58; (2) transfer 1111 from register 64 to converter63; (3) clear register 56; and (4) set shift register 61 to 01000.

When sequencer 53 advances to step six, register 61 is again shifted,this time to 10000. The one in the most significant digit is sensed toopen gates 62, whereby the binary code 0000, the least four significantbits in register 61, is applied as the divisor to divider 59. Since thecode 0000 divides the divider input by 1, the difierence is stored asthe slope 111 by divider 59.

In response to the seventh timing pulse, the 1U count converted to andstored as an analog voltage in converter 63 is compared with the slopeof deriving from divider 59. Since 1U is greater than no output isderived from comparer 62 on lead 66 and gate A is not enabled. At thesame time, the maximum permissible, predetermined increment or issupplied to register 56.

Sequencer 53 is now advanced to stage eight when converter 63 is clearedand the y y contents of accumulator 53.1 are decremented by on, so theaccumulator thereafter stores y -y a. Step nine is now reached and the0000, m contents of register 65 are transferred to converter 63.

The tenth timing pulse is now generated to permit enabling of gate A ifthe m output of divider 59 is less than the m output of converter 63, asdetermined by a pulse on lead 67. Since m m point y lies within thespecified lower limit and gate A is not enabled.

In response to sequencer 53 reaching state 11, converter 58 is clearedand the y signal in coder 51 is transferred to register 55.1. Sinceprogrammer 53 has reached this point, it has been established that y iswithin the limits set by 1U and IL. It is necessary to now determine theslopes of the new limiting lines 2U and 2L. Point y is now loaded intoregister 55.1 so that it can be stored and readout if the line between yand y is outside the boundary established by 2U and 2L.

Step twelve of timer 53 is now attained causing (1) transfer of (y y -u)from accumulator 53.1 to converter 58; (2) register 56 to be cleared;(3) disabling of gate 52; and (4) enabling of gate 61.1. Since divider59 now has as an analog input y y a and a digital code 0000, it derivesa voltage proportional to This voltage is applied to coder 51 via gate61 and is converted into a binary number by the coder when timer 53reaches step 13.

It is now necessary to determine if 2L 1L, i.e. ascertain if thesuccessive limits or fans are converging. This is accomplished bycomparing the 2L output of divider 59 and the IL output 'of converter 63in circuit 62. Since 2L 1L, a binary one is derived on lead 67, causingAND gate A to be enabled since timer 53 has now reached state fourteen.Enabling gate A transfers 2L to register 65 from coder 51. At the sametime, number register 56 is set to 20:.

The fifteenth pulse is now generated causing the 204 number loaded inregister 56 to be added to the y y u contents of accumulator 53, wherebythe accumulator is set to y y +a. Simultaneously, converters 58 and 63are cleared so that they are respectively loaded with (y y +a) and 1Uwhen the sixteenth timing pulse is derived. At this time, the output ofdivider 59 is proportional to In response to timer 53 being advanced tostate seventeen, coder 51 converts m into a binary number that is storedin register 64 when timing pulse eighteen occurs, since m m The m mdecision is made by gate A responsive to the binary one output on lead66 that is derived whenever the output of converter 63 exceeds that ofdivider 59. Since timer 53 has reached step 18, it resets itself to stepone and closes gate 61.

With sequencer 53 at its first stage, clearance of accumulator 53.1,register 56, converters 58 and 63 is effected. Analog gate 52 is againenabled and counter 64 is advanced from 00001 to 00010. The secondtiming pulse is now generated, whereby the y analog sample is coded aswell as stored by coder 51 and 00010 is transferred from counter 64 toregister 61.

In response to the third timing pulse, 5 goes from coder 51 toaccumulator 53.1, y is transferred between registers 57 and 56 andregister 61 is shifted to 00100. Sequencer 53 now advances to stagefour, whereby accumulator 53.1 stores y -y and register 61 shifts to01000. When stage five is reached, y y goes from accumulator 53.1 toconverter 58, 2U goes from shift register 64 to converter 63 andregister 56 is cleared. At the same time, register 61 is shifted to10000 and the 0000 code is loaded into divider 59. When the sixth pulseis generated, AND gate 65 is inhibited by the ONE in the mostsignificant stage of shift register 61. However, AND gate 71 is enabledby the binary code 10000 in shift register 61 and allows the sixth pulseto shift both the upper and lower slope shift registers 64.1 and 65,respectively, to the left one place. This action has left the code 0000in the least significant bit positions of shift register 61, which codeis read into divider 59 via gates 62.1. In consequence, the analog inputto divider 59 is divided by one, as previously. The signal deriving fromdivider S9 is compared with a signal deriving from converter 63 thatrepresents twice the slope of signals previously derived from it. Thisis because the numbers stored in registers 64.1 and 65 are shifted leftone place (i.e. doubled) in response to the 10000 code in register 61.Of course, doubling the slope signals in registers 65 and 64.1 has thesame effect as dividing the dividend input or quotient output of divider59. Since the remaining sequences for investigating points y and y., aresubstantially the same as those discussed supra, it is not believednecessary to present a complete sequence for them.

The only distinction for investigating y, with respect to y occurs atstep 14, utilized to determine if m m Since m m the latter slope, asstored in coder 51, is not transferred into register 65, which insteadretains m This is determined by comparator 62. Since m m the output ofconverter 63 exceeds that of divider 59 and lead 67 is not energizedwhen timing pulse fourteen is derived. In consequence, gate A is notenabled and register 65 is not coupled to coder 51.

The investigation of 1 to determine if 3 should be transmitted is asdescribed above in connection with y until step ten is reached. At thistime, a determination is made by gate A that the m output of divider 59is less than the m limit stored in register 65. Such a relation betweenthe slopes indicates that 3 is outside the permissible fan limit lines.Gate A is thereby energized in response to the signal on lead 67 and thetenth timing pulse is generated to advance timer 53 to stage nineteen.

With timer 53 so set, the non-redundant y signal stored in register 55.1is read out to the transmitter and into register 57 as the originalsample for the next computation cycle. Counter 64 and shift register 61are reset to counts of 00001, registers 64 and 65 are reset to 1U andIL, respectively, and accumulator 53.1 as well as register 56 arecleared. A new computation cycle is thus ready to begin when timer 53advances from stage nineteen to three with 3 in coder 51, y.; inregister 57 and each of the other components in the system energizedexactly as when y and y were loaded in register 57 and coder 51.

If m were greater than the m indication stored in register 64, step 10is never reached by sequencer 53. Instead, at step seven comparator 62generates an output that is sampled by gate A to advance timer 53 tostate nineteen and the same sequence of operations as indicated supra isfollowed.

It should be noted that if more than one input parameter is involved, asin the case of time division multiplex data, registers 55.1, 57, 61, 64and 65 of FIG. 2 can be loaded with numbers from a memory that steps insequence with the multiplexer. Thus, each parameter would have its ownnumbers for these five registers. The new values of these numbers wouldbe stored following each set of calculations for each parameter andapparatus, in the form of additional sequencer steps, must be providedto transfer the time count to counter 64 at the beginning of each cycle.

While we have described and illustrated one specific embodiment of ourinvention, it will be clear that variations of the details ofconstruction which are specifically illustrated and described may beresorted to without departing from the true spirit and scope of theinvention as defined in the appended claims. For instance, under certainconditions, a binary divider can be substituted for the converters 58,63 and divider 59.

I claim:

I. In a telemetering system for transmitting data indicative of amonitored signal to a remote location comprising means responsive tosaid signal for establishing a function having a straight line law ofvariation, said function including a time, amplitude point on saidsignal and the values between a pair of successive upper and lowerlimiting lines including said point, and means responsive to said signaland said function for reading out another time, amplitude point on saidsignal only when the value of said function differs from the value ofthe signal by at least a redetermined amount.

2. In a telemetering system for transmitting data indicative of amonitored signal to a remote location comprising means responsive tosaid signal for establishing a function having a straight line law ofvariation, said function including a time, amplitude point on saidsignal and the values between a pair of successive upper and lowerlimiting lines including said point, and means responsive to said signaland said function for reading out another time, amplitude point on saidsignal only when the value of said function differs from the value ofthe signal by at least a predetermined amount, said limiting linesconverging to a line determined by the value of said signal.

3. In a telemetry system for transmitting data indicative of a monitoredsignal to a remote location, comprising means for sampling the values ofsaid data y y y at predetermined time intervals 1 t t means responsiveto said sampling means for establishing a plurality of upper and lowerlimit lines 1U, 1L, 2U, 2L, NU, NL, each of said lines including thepoint y the kth upper limit line, KU, including the point y -i-ot, thekth lower limit line, KL, including the point y 0t, where oz is apredetermined value and K is any integer between 1 and N, meansresponsive to said slopes and y for deriving a set of permissible valueshaving said limiting lines as its outer boundary, and means for derivingan indication when y is outside said set of permissible values.

4. The system of claim 3 further including means for reading out y andadjusting the value of y to y only in response to the derivation of saidindication.

5. The system of claim 3 further including means responsive to KU and KLfor computing the slopes of the lower and upper limit lines, and meansresponsive to the computed slope values for always converging saidpermissible values into a set approaching a straight line.

No references cited.

NEIL C. READ, Primary Examiner.

THOMAS B. HABECKER, Examiner.

1. IN A TELEMETERING SYSBEM FOR TRANSMITTING DATA INDICATIVE OF AMONITORED SIGNAL TO A REMOTE LOCATION COMPRISING MEANS RESPONSIVE TOSAID SIGNAL FOR ESTABLISHING A FUNCTION HAVING A STRIGHT LINE LAW OFVARIATION, SAID FUNCTION INCLUDING A TIME, AMPLITUDE POINT ON SAIDSIGNAL AND THE VALUES BETWEEN A PAIR OF SUCCESSIVE UPPER AND LOWERLIMITING LINES NCLUDING SAID POINT, AND MEANS RESPONSIVE TO SAID SIGNALAND SAID FUNCTION FOR READING OUT ANOTHER TIME, AMPLITUDE POINT ON SAIDSIGNAL ONLY WHEN THE VALUE OF SAID FUNCTION DIFFERS FROM THE VALUE OFTHE SIGNAL BY AT LEAST A PREDETERMINED AMOUNT.